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<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>BRAA, BRAAZ, BRAB, BRABZ -- A64</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">BRAA, BRAAZ, BRAB, BRABZ</h2>
      <p class="aml">Branch to Register, with pointer authentication. This instruction authenticates the address in the general-purpose register that is specified by &lt;Xn&gt;, using a modifier and the specified key, and branches to the authenticated address.</p>
      <p class="aml">The modifier is:</p>
      <ul>
        <li>In the general-purpose register or stack pointer that is specified by &lt;Xm|SP&gt; for <span class="asm-code">BRAA</span> and <span class="asm-code">BRAB</span>.</li>
        <li>The value zero, for <span class="asm-code">BRAAZ</span> and <span class="asm-code">BRABZ</span>.</li>
      </ul>
      <p class="aml">Key A is used for <span class="asm-code">BRAA</span> and <span class="asm-code">BRAAZ</span>. Key B is used for <span class="asm-code">BRAB</span> and <span class="asm-code">BRABZ</span>.</p>
      <p class="aml">If the authentication passes, the PE continues execution at the target of the branch. For information on behavior if the authentication fails, see <a class="armarm-xref" title="Reference to Armv8 ARM section">Faulting on pointer authentication</a>.</p>
      <p class="aml">The authenticated address is not written back to the general-purpose register.</p>
    
    <h3 class="classheading"><a id="iclass_general"/>Integer<span style="font-size:smaller;"><br/>(FEAT_PAuth)
          </span></h3><p class="desc"/><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td>1</td><td>0</td><td>1</td><td>0</td><td>1</td><td class="r">1</td><td class="lr">Z</td><td class="lr">0</td><td class="l">0</td><td class="r">0</td><td class="l">1</td><td>1</td><td>1</td><td>1</td><td class="r">1</td><td class="l">0</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">1</td><td class="lr">M</td><td colspan="5" class="lr">Rn</td><td colspan="5" class="lr">Rm</td></tr><tr class="secondrow"><td colspan="7"/><td/><td/><td colspan="2" class="droppedname">op</td><td colspan="5"/><td colspan="4"/><td class="droppedname">A</td><td/><td colspan="5"/><td colspan="5"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding">Key A, zero modifier<span class="bitdiff"> (Z == 0 &amp;&amp; M == 0 &amp;&amp; Rm == 11111)</span></h4><a id="BRAAZ_64_branch_reg"/><p class="asm-code">BRAAZ  <a href="#sa_xn" title="64-bit general-purpose register holding address to be branched to (field &quot;Rn&quot;)">&lt;Xn&gt;</a></p></div><div class="encoding"><h4 class="encoding">Key A, register modifier<span class="bitdiff"> (Z == 1 &amp;&amp; M == 0)</span></h4><a id="BRAA_64P_branch_reg"/><p class="asm-code">BRAA  <a href="#sa_xn" title="64-bit general-purpose register holding address to be branched to (field &quot;Rn&quot;)">&lt;Xn&gt;</a>, <a href="#sa_xm_sp" title="64-bit general-purpose source register or SP holding modifier (field &quot;Rm&quot;)">&lt;Xm|SP&gt;</a></p></div><div class="encoding"><h4 class="encoding">Key B, zero modifier<span class="bitdiff"> (Z == 0 &amp;&amp; M == 1 &amp;&amp; Rm == 11111)</span></h4><a id="BRABZ_64_branch_reg"/><p class="asm-code">BRABZ  <a href="#sa_xn" title="64-bit general-purpose register holding address to be branched to (field &quot;Rn&quot;)">&lt;Xn&gt;</a></p></div><div class="encoding"><h4 class="encoding">Key B, register modifier<span class="bitdiff"> (Z == 1 &amp;&amp; M == 1)</span></h4><a id="BRAB_64P_branch_reg"/><p class="asm-code">BRAB  <a href="#sa_xn" title="64-bit general-purpose register holding address to be branched to (field &quot;Rn&quot;)">&lt;Xn&gt;</a>, <a href="#sa_xm_sp" title="64-bit general-purpose source register or SP holding modifier (field &quot;Rm&quot;)">&lt;Xm|SP&gt;</a></p></div><p class="pseudocode">integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rn);
integer m = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Rm);
boolean use_key_a = (M == '0');
boolean source_is_sp = ((Z == '1') &amp;&amp; (m == 31));

if !<a href="shared_pseudocode.html#impl-aarch64.HavePACExt.0" title="function: boolean HavePACExt()">HavePACExt</a>() then
    UNDEFINED;

if Z == '0' &amp;&amp; m != 31 then
    UNDEFINED;</p>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Xn&gt;</td><td><a id="sa_xn"/>
        
          <p class="aml">Is the 64-bit name of the general-purpose register holding the address to be branched to, encoded in the "Rn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Xm|SP&gt;</td><td><a id="sa_xm_sp"/>
        
          <p class="aml">Is the 64-bit name of the general-purpose source register or stack pointer holding the modifier, encoded in the "Rm" field.</p>
        
      </td></tr></table></div><div class="syntax-notes"/>
    <div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3>
      <p class="pseudocode">bits(64) target = <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];

bits(64) modifier = if source_is_sp then <a href="shared_pseudocode.html#impl-aarch64.SP.read.0" title="accessor: bits(64) SP[]">SP</a>[] else <a href="shared_pseudocode.html#impl-aarch64.X.read.2" title="accessor: bits(width) X[integer n, integer width]">X</a>[m, 64];

if use_key_a then
    target = <a href="shared_pseudocode.html#impl-aarch64.AuthIA.3" title="function: bits(64) AuthIA(bits(64) x, bits(64) y, boolean is_combined)">AuthIA</a>(target, modifier, TRUE);
else
    target = <a href="shared_pseudocode.html#impl-aarch64.AuthIB.3" title="function: bits(64) AuthIB(bits(64) x, bits(64) y, boolean is_combined)">AuthIB</a>(target, modifier, TRUE);

// Value in BTypeNext will be used to set PSTATE.BTYPE
if InGuardedPage then
    if n == 16 || n == 17 then
        BTypeNext = '01';
    else
        BTypeNext = '11';
else
    BTypeNext = '01';
<a href="shared_pseudocode.html#impl-shared.BranchTo.3" title="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(target, <a href="shared_pseudocode.html#BranchType_INDIR" title="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_INDIR</a>, FALSE);</p>
    </div>
  <hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
      Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved.
      This document is Non-Confidential.
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